Semiconductor device

ABSTRACT

A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of, and claims priority to, U.S.patent application Ser. No. 13/899,916 filed on May 22, 2013, and whichclaims priority to Japanese patent application No. 2012-122288, filed onMay 29, 2012, the disclosure of each of the above-referencedapplications is incorporated herein.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device which useshigh-k [high-dielectric constant] materials as a gate insulating film.

BACKGROUND

It is necessary to suppress a gate leak current, and to decrease EOT(Equivalent Oxide Thickness) to develop a technological advance andmicrofabrication in transistors of semiconductor devices such as DRAM.Therefore, the semiconductor devices using high-dielectric constantmaterials (High-k materials) as a gate insulating film are developed(for example, refer to JP Patent Kokai Publication No. JP-P2011-14689A(Patent Literature 1) which corresponds to US2012/080756A1 and JP PatentKokai Publication No. JP-P2011-49282A (Patent Literature 2)).

A semiconductor device which is described in Patent Literature 1 isprovided with a high dielectric gate insulating film which is formed ona substrate and a metal gate electrode which is formed on the highdielectric gate insulating film, and a halogen segregates on a metalgate electrode side at an interface between the high dielectric gateinsulating film and the metal gate electrode.

In a semiconductor device which is described in Patent Literature 2, agate structure having a high dielectric constant film and a metal gateelectrode is formed on a semiconductor substrate in a MONOS memoryforming area and a MISFET area.

SUMMARY

The following analyses are given according to the views of the presentdisclosure.

If a thickness of a gate insulating film which has a low relativedielectric constant such as a silicon oxide film be increased, this willacts against a trend of the microfabrication of semiconductor devices,EOT will increase, and an on-electric current will decrease. On theother hand, with the miniaturization of the semiconductor device, a gateleak current will increase if a gate insulating film having the lowrelative dielectric constant be thinned. Therefore it is necessary touse a gate insulating film having a high relative dielectric constant inorder to suppress a gate leak current and increase on-electric current.However, high dielectric constant materials such as hafnium oxide (HfO2)are thermally unstable materials in comparison with silicon oxide(SiO2), and a compound containing hafnium (hereinafter referred to as“hafnium-containing compound”.) such as hafnium oxide is crystallized bythe heat-treatment of a comparatively low temperature in a process ofmanufacture. Particularly, the more the relative dielectric constant ofthe high dielectric material increases, the more the crystallizationtemperature lowers. When the high dielectric material in the gateinsulating film crystallizes, a threshold voltage cannot be controlledor becomes easy to vary. Furthermore, hafnium oxide becomes easy toreact with the metal gate electrode and silicon substrate, and the leakcurrent increases. Furthermore, there arise problems that causereliability degradation of the gate insulating film.

In the technique described in Patent Literature 2, in order to preventthe degradation of the high dielectric material caused by the heattreatment for activation of source/drain regions, a dummy gate electrodeis formed, followed by forming the source/drain regions and removing thedummy gate electrode, then the high dielectric constant gate insulatingfilm and the metal gate electrode are formed on the semiconductorsubstrate. However, as described below, this method cannot be applied toa manufacturing process of a semiconductor device having a buried wordline.

In the manufacturing process of the semiconductor device having theburied word line, a gate structure of a memory cell region is formedprior to that of a peripheral circuit region. That is, when the highdielectric constant gate insulating film containing thehafnium-containing compound is formed in both of the peripheral circuitregion and the memory cell region, the semiconductor substrate isexposed in the peripheral circuit region, and the gate insulating film(interface layer) of a silicon oxide film is formed in the peripheralcircuit region by thermal oxidation after the buried word line using thehigh dielectric constant gate insulating film is formed in the memorycell region. Then, the gate structure having the high dielectricconstant gate insulating film and the metal gate electrode is formed onthe interface layer. However, at the time of the heat-treatment to formthe interface layer, since the high dielectric constant gate insulatingfilm has been already formed in the memory cell region, thisheat-treatment incurs a thermal load on the high dielectric constantgate insulating film in the memory cell region. And, by this thermalload, the hafnium-containing compound crystallizes in the highdielectric constant gate insulating film of the memory cell region, andthe problems in the thinning of the equivalent gate oxide thickness, theincrease of the gate leak current and the rise of the threshold voltageoccur, resulting in a decrease in the on-electric current of the memorycell region. And, by this thermal load, the hafnium-containing compoundcrystallizes in the high dielectric constant gate insulating film of thememory cell region, the problems such as the increase in the gate leakcurrent, the uncontrollability of the threshold voltage, and thereliability degradation occurs.

According to a first aspect of the present disclosure, there is provideda semiconductor device comprising a memory cell region having a firsttransistor, and a peripheral circuit region which is formed around thememory cell region and has a second transistor on a semiconductorsubstrate. The first transistor has a first source electrode and a firstdrain electrode which are formed on the semiconductor substrate, a firstburied gate insulating film which is formed along an inner wall of atrench formed in the semiconductor substrate between the first sourceelectrode and the first drain electrode and whose relative dielectricconstant is higher than a relative dielectric constant of silicon oxide,and a buried gate electrode which is formed in the trench on the firstburied gate insulating film, comprises metal and functions as a wordline. The second transistor has a second source electrode and a seconddrain electrode which are formed on the semiconductor substrate, a firston-substrate gate insulating film which is formed on a surface of thesemiconductor substrate between the second source electrode and thesecond drain electrode and whose relative dielectric constant is higherthan a relative dielectric constant of silicon oxide, and anon-substrate gate electrode which is formed on the first on-substrategate insulating film and comprises metal. The first buried gateinsulating film and the first on-substrate gate insulating film comprisea compound containing hafnium. A first Hf content percentage, which is acontent percentage of hafnium in the first buried gate insulating film,is different from a second Hf content percentage, which is a contentpercentage of hafnium in the first on-substrate gate insulating film.

According to a second aspect of the present disclosure, there isprovided a semiconductor device comprising a first transistor and asecond transistor on a semiconductor substrate. The first transistorincludes a first gate insulating film which is formed along an innerwall of a trench formed in the semiconductor substrate and whoserelative dielectric constant is higher than a relative dielectricconstant of silicon oxide, and a first gate electrode which is buried inthe trench and formed on the first gate insulating film, and comprisesmetal. The second transistor includes a second gate insulating filmwhich is formed on a most upper surface of the semiconductor substrateand whose relative dielectric constant is higher than a relativedielectric constant of silicon oxide, and a second gate electrode whichis formed on the second gate insulating film and comprises metal. Thefirst gate insulating film and the second gate insulating film comprisea compound containing hafnium (hereinafter referred to as“hafnium-containing compound”). A first Hf content percentage, which isa content percentage of hafnium in the first gate insulating film, isdifferent from a second Hf content percentage, which is a contentpercentage of hafnium in the second gate insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of a memory cell region in asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 2 is a schematic cross-sectional view of a memory cell region in asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 3 is a schematic cross-sectional view of a memory cell region in asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 4 is a schematic cross-sectional view of a peripheral circuitregion in a semiconductor device according to a first exemplaryembodiment of the present disclosure.

FIG. 5 a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 6 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 7 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 8 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 9 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 10 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 11 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 12 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 13 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 14 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 15 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 16 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 17 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 18 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 19 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 20 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 21 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

FIG. 22 is a schematic flowchart to explain a method for manufacturing asemiconductor device according to a first exemplary embodiment of thepresent disclosure.

DETAILED DESCRIPTION

It is explained a semiconductor device according to a first exemplaryembodiment of the present disclosure with DRAM as an example. Thesemiconductor device has a memory cell region 100A and a peripheralcircuit region 100B. FIG. 1 shows a schematic plan view of the memorycell region in the semiconductor device according to the first exemplaryembodiment of the present disclosure. In FIG. 1, a part of elementsis/are illustrated. FIG. 1 is a drawing to make positional relationsamong the elements clear, and each element is made transparence.Furthermore, some elements in FIG. 1 are hatched for clarification. FIG.2 and FIG. 3 show schematic cross-sectional views of the memory cellregion in the semiconductor device according to the first exemplaryembodiment of the present disclosure. FIG. 2 is the schematiccross-sectional view taken along a line II-II of FIG. 1. FIG. 3 is theschematic cross-sectional view taken along a line III-III of FIG. 1.FIG. 4 shows a schematic cross-sectional view of the peripheral circuitregion in the semiconductor device according to the first exemplaryembodiment of the present disclosure. In addition, in FIG. 2 throughFIG. 4, the elements such as a stopper film and a side wall are notillustrated. Furthermore, in the following explanation, reference signsof the drawings are added for helping better understanding of thedisclosure, without intention to limit to the illustrated modes.

At first the memory cell region 100A is explained. The memory cellregion 100A has a plurality of bit lines 161, and a plurality of wordlines 163 and a buried wiring 164 for element isolation which are atright angles to the bit lines 161, and a plurality of active regions(impurity diffusion layers) 101 a which extend so as to intersect thebit the lines 161 and the word lines 163, and impurity highconcentration diffusion layers 101 d which are formed on both sides ofthe word line 163 of the semiconductor substrate 101 and serve as afirst source electrode and a first drain electrode.

The word line 163 is a buried gate electrode which is buried in a grooveformed in the semiconductor substrate 101. The word line 163 has asecond buried gate insulating film 115 which covers an inner wall of thegroove formed in the semiconductor substrate 101, a first buried gateinsulating film 116 which is laminated on the second buried gateinsulating film 115, and a first metal gate electrode 118 which isformed on the first buried gate insulating film 116 and is buried in atleast part of the groove.

As the second buried gate insulating film 115, for example, a siliconoxide film or a silicon oxynitride film can be used.

For a material of the first buried gate insulating film 116, a materialhaving a higher relative dielectric constant than that of silicon oxideis used. As the first buried gate insulating film 116, a materialcontaining hafnium, such as hafnium silicate (HfxSiyOz, HfxSiyOzNw) maybe used. It is preferred that a first Hf content percentage, which is acontent percentage of Hf in the first buried gate insulating film 116,(=[the number of hafnium atoms per one molecule of hafnium-containingcompound]/([the number of hafnium atoms per one molecule ofhafnium-containing compound]+[the number of silicon atoms per onemolecule of hafnium-containing compound])×100) is a content percentageof Hf that does not cause crystallization by heat treatment (heattreatment when an oxide film is formed (e.g., 700 degrees Celsius to1,200 degrees Celsius)) in a manufacturing process. For example, it ispreferred that the first content percentage of Hf in the first buriedgate insulating film 116 is 10 atm % to 90 atm %. When the first contentpercentage of Hf is not less than 10 atm %, while suppressing the gateleakage, the thinner equivalent oxide thickness can be achieved. On theother hand, the hafnium-containing compound crystallizes in theoxidation treatment of the process when the first content percentage ofHf is beyond 90 atm %. Considering relation between easiness of thecrystallization and securing of the EOT, from the viewpoint ofprevention of the leak current, it is preferred that the first contentpercentage of Hf is not less than 20 atm %, and preferably not less than40 atm %. And it is preferred that the first content percentage of Hf isnot more than 80 atm %, and preferably not more than 60 atm %. In thepresent disclosure, for example, the Hf content percentage of theinsulating film can be measured by using X-rays photoelectronspectroscopy (XPS).

It is preferred that for a film thickness of the first buried gateinsulating film 116 is 1 nm to 3.5 nm from the viewpoint of preventionof the crystallization.

As a material of the first metal gate electrode 118, for example,titanium nitride (TiN), tungsten nitride (WN), tungsten (W) and so oncan be used.

In FIG. 3, a first exposed part 166 and a second exposed part 167, whichexpose the high-concentration impurity diffusion layer 101 d of thesemiconductor substrate 101 from insulating films such as the secondburied gate insulating film 115 covering the semiconductor substrate101, are formed on both sides of the word line 163. In the first exposedpart 166, a contact plug 162 is electrically connected to thehigh-concentration impurity diffusion layer 101 d. In the mode shown inFIG. 3, the contact plug 162 has a fourth polysilicon film 138 which isformed on the high-concentration impurity diffusion layer 101 d, and asecond conductive film 139 which is laminated on the fourth polysiliconfilm 138. The contact plug 162 is also electrically connected to acontact pad 141. The contact pad 141 is formed on the second conductivefilm 139. In the second exposed part 167 which is exposed from anopening 165 formed on a region between adjacent word lines 163, the bitline 161 is electrically connected to the high-concentration impuritydiffusion layer 101 d. In the mode shown in FIG. 3, the bit line 161 hasa third polysilicon film 134 which is formed on the high-concentrationimpurity diffusion layer 101 d, and a first conductive film 135 which islaminated on the third polysilicon film 134. A third insulating film 136such as a silicon nitride film lies between the first conductive film135 and the contact pad 141. A first interlayer insulating film 140exists around the bit line 161 and contact plug 162.

A capacitor 168 is connected on the contact pad 141. The capacitor 168is formed in a second interlayer insulating film 145. The capacitor 168has a lower electrode 142 which is formed into a pipe shape, adielectric film 143 which coats an inner wall of the lower electrode142, and an upper electrode 144 buried on the dielectric film 143.

A third interlayer insulating film 146 is formed on the capacitor 168.An upper wiring 147 is formed on the third interlayer insulating film146. The upper wiring 147 is coated with a protective film 148.

Then, the peripheral circuit region 100B is explained. In the peripheralcircuit region 100B, a p well 101 b and n well 101 c are formed in thesemiconductor substrate 101, and an n-type impurity diffusion layer 101e is formed in the p well 101 b, and a p-type impurity diffusion layer101 f is formed in the n well 101 c. A first transistor 171 is formed inthe p well 101 b, and a second transistor 172 is formed in the n well101 c.

The first transistor 171 has an n-type impurity diffusion layer 101 ewhich serves as the source electrode and the drain electrode, and athird on-substrate gate insulating film 122 such as a silicon oxide filmand so on, a first on-substrate gate insulating film 123 which islaminated on the third on-substrate gate insulating film 122, and asecond metal gate film 124 which is laminated on the first on-substrategate insulating film 123. The second transistor 172 has a p-typeimpurity diffusion layer 101 f which serves as the source electrode andthe drain electrode, the third on-substrate gate insulating film 122such as the silicon oxide film and so on, the first on-substrate gateinsulating film 123 which is laminated on the third on-substrate gateinsulating film 122, a second on-substrate gate insulating film 128which is laminated on the first on-substrate gate insulating film 123,and a third metal gate film 129 which is laminated on the secondon-substrate gate insulating film 128.

On the metal gate films 124 and 129 on the first transistor 171 and thesecond transistor 172, a third polysilicon film 134, the firstconductive film 135 and the third insulating film 136 are laminated.

As materials of the first on-substrate gate insulating film 123 and thesecond on-substrate gate insulating film 128, materials having a higherrelative dielectric constant than that of silicon oxide are used. As thefirst on-substrate gate insulating film 123, hafnium containingmaterials such as hafnium oxide (HfO2, HfON), hafnium silicate (HfSiO,HfSiON) and so on may be used. And, as the second on-substrate gateinsulating film 128, Al2O3 may be used, for example. It is possible tolower the voltage by forming the second on-substrate gate insulatingfilm 128.

It is preferred that a second Hf content percentage, which is a contentpercentage of Hf in the first on-substrate gate insulating film 123, anda thickness of the hafnium-containing compound are determined so thatthe crystallization of hafnium-containing compound is not caused by heattreatment in a manufacturing process, particularly by heat treatment atthe time of formation for the gate stack of the peripheral circuitregion. Since in the heat-treatment after the formation of thetransistor of the peripheral circuit region, temperature is lower ortime is shorter than that of the heat-treatment that is necessary forthe formation of the third on-substrate insulating film, the Hf contentcan be raised than that of the first buried insulating film of thememory cell region.

On the other hand, from the viewpoint of the equivalent oxide thickness,it is preferred that the second Hf content percentage of the firston-substrate gate insulating film 123 is different from the first Hfcontent percentage of the first buried gate insulating film 116 in thememory cell region 100A, and preferably higher than the first Hf contentpercentage. Furthermore, it is more preferred that the second Hf contentpercentage is higher than the first Hf content percentage by 10 atm % ormore. For example, when the first Hf content percentage in the firstburied gate insulating film 116 in the memory cell region 100A is 50 atm%, the second Hf content percentage of the first on-substrate gateinsulating film 123 in the peripheral circuit region 100B can be set to60 atm %. And, when the first Hf content percentage in the first buriedgate insulating film 116 in the memory cell region 100A is 60 atm %, thesecond Hf content percentage of the first on-substrate gate insulatingfilm 123 in the peripheral circuit region 100B can be set to 100 atm %.But, it is necessary that the film thickness is determined so that thehafnium-containing compound does not crystallize. By doing this way, theEOT of the transistor of the peripheral circuit region can be decreased,and on-state current can be increased. In addition, the calculationmethod of the second Hf content percentage is similar to that of thefirst Hf content percentage. In the case of hafnium oxide (HfO2, HfON),the Hf content percentage is 100 atm %.

In the present disclosure, in the memory cell region having the buriedword line structure, the high dielectric constant film is used as thegate insulating film, and metal is used for the gate electrode.Therefore, the on-state current flowing through a channel can beincreased, and the processing speed of the semiconductor device can beaccelerated.

And, in the present disclosure, the first Hf content percentage of thehigh dielectric constant film in the memory cell region 100A having theburied word line structure is lowered, and a deterioration caused by thecrystallization of the hafnium-containing compound in the gateinsulating film is restrained. Therefore, the problems of the increaseof the equivalent oxide thickness in the transistor of the memory cellregion 100A, the increase of the gate leak current, and the increase inthe threshold voltage are prevented, thus, the on-state current can beincreased. Furthermore, a variation and the increase in the thresholdvoltage also can be restrained. Furthermore, a short circuit by thecrystallization of the hafnium-containing compound also can beprevented. And, an ability of the transistor of the peripheral circuitregion can be improved because the material having high relativedielectric constant is used without the crystallization of thehafnium-containing compound in the peripheral circuit region.

A manufacturing method of a semiconductor device according to the firstexemplary embodiment of the present disclosure is explained. In FIGS.5-22, schematic flowcharts to explain the method for manufacturing thesemiconductor device according to the first exemplary embodiment of thepresent disclosure are shown. In FIGS. 5-22, Fig. A is a cross-sectionalview of a region corresponding to FIG. 2, namely, a drawingcorresponding to a cross-section along a line II-II of FIG. 1 in thememory cell region of the semiconductor device according to the firstexemplary embodiment of the present disclosure. Fig. B is across-sectional view of a region corresponding to FIG. 3, namely, adrawing corresponding to a cross-section along a line III-III of FIG. 1in the memory cell region of the semiconductor device according to thefirst exemplary embodiment of the present disclosure. Fig. C is across-sectional view of a region corresponding to FIG. 4, namely, adrawing corresponding to a cross-section in the peripheral circuitregion of the semiconductor device according to the first exemplaryembodiment of the present disclosure.

On a semiconductor substrate 101, a first mask 103 and a second mask 104which have a pattern of a desired shape are formed. The first mask 103may be, for example, a silicon oxide film. The second mask 104 may be,for example, a silicon nitride film. Then, in a memory cell region 100Aand a peripheral circuit region 100B, the semiconductor substrate 101 isetched using the first mask 103 and the second mask 104 as masks, anelement isolating groove 102 for forming of an element isolating film isformed (FIG. 5).

Then, in the memory cell region 100A and the peripheral circuit region100B, a first protective film 105 is formed on the entire surface. Asthe first protective film 105, for example, a silicon oxide film may beused. Then, a first element isolating film 106 is buried in the elementisolating groove 102 of the memory cell region 100A, by covering thememory cell region 100A with an insulating film and performing anetchback (FIG. 6). As the first element isolating film 106, for example,a silicon nitride film may be used.

Then, a second element isolating film 107 is buried on the first elementisolating film 106, and a third element isolating film 108 is buried inthe element isolating groove 102 of the peripheral circuit region 100B.As the second element isolating film 107 and the third element isolatingfilm 108, a silicon oxide film may be used. Then, the surface isflattened by a CMP (Chemical Mechanical Polishing) method or the like.On this occasion an exposed part of the first protective film 105 isremoved (FIG. 7).

Then, a second protective film 109 is formed on the entire surface ofthe memory cell region 100A and the peripheral circuit region 100B,after the first mask 103 and the second mask 104 are removed. Forexample, the second protective film 109 may be a silicon oxide filmformed by a thermal oxidation. Then, an impurity diffusion layer 101 ais formed by implanting an impurity into the semiconductor substrate 101of the memory cell region 100A. For example, using phosphorus as theimpurity, an n-type impurity diffusion layer 101 a can be formed. And,in the peripheral circuit region 100B, the impurities are implanted, anda p-well 101 b and an n-well 101 c are formed, respectively (FIG. 8).

Then, in the memory cell region 100A, the semiconductor substrate 101 inthe region to form a gate electrode groove in a later process isexposed, and a third mask 110 and a fourth mask 111 are laminated on thesecond protective film 109 (FIG. 9). As the third mask 110, for example,a silicon nitride film may be used. As the fourth mask 111, for example,a carbon film may be used.

Then, the semiconductor substrate 101 of the memory cell region 100A isetched using the third mask 110 and the fourth mask 111 as masks, a gateelectrode groove 112 to form an buried gate electrode is formed. Then,the fourth mask 111 is removed (FIG. 10).

Then, a second buried gate insulating film 115 and a first buried gateinsulating film 116 are laminated on the entire surface of the memorycell region 100A and the peripheral circuit region 100B (FIG. 11). Asdescribed above, a first Hf content percentage of the first buried gateinsulating film 116 is made lower than a second Hf content percentage ofa high dielectric constant film to be formed in the peripheral circuitregion 100B in a later process. An on-state current can be increased byusing the high dielectric constant film as the gate insulating film.

Then, a first metal gate film 117 is formed in the entire surface of thememory cell region 100A and the peripheral circuit region 100B (FIG.12). An on-state current can be increased by forming a gate electrode ofmetal not polysilicon.

Then, the first metal gate film 117 is formed and processed, and a firstmetal gate electrode 118 is formed in the gate electrode groove 112 ofthe memory cell region 100A (FIG. 13). In the peripheral circuit region100B, the first metal gate film 117 is removed.

Then, an insulating film is buried in the gate electrode groove 112(FIG. 14). For example, a buried cap insulating film 119 in a linearform is formed on the entire surface of the memory cell region 100A andthe peripheral circuit region 100B, and a first insulating film 120 isburied in the gate electrode groove 112. As the buried cap insulatingfilm 119, for example, a silicon nitride film may be used. As the firstinsulating film 120, a SOD (Spin-on Dielectrics) film may be used.

Then, a part of the insulating film above the impurity diffusion layer101 a is removed (FIG. 15). For example, in the memory cell region 100A,the upper parts of the buried cap insulating film 119 and the firstinsulating film 120 are removed by dry etching, and the third mask isremoved by wet etching. And, in the peripheral circuit region 100B, theburied cap insulating film 119 and the first insulating film 120 areremoved by dry etching, and the third mask is removed by wet etching.Furthermore, in the peripheral circuit region 100B, the first buriedgate insulating film 116 and the second buried gate insulating film 115are also removed.

Then, a second insulating film 121 acting as an interlayer insulatingfilm and as a protective film for the memory cell region 100A is formedon the entire surface of the memory cell region 100A and the peripheralcircuit region 100B (FIG. 16). As the second insulating film 121, forexample, a silicon nitride film and a silicon oxynitride film may beused.

Then, in the peripheral circuit region 100B, the second protective film109 and the second insulating film 121 are removed, for example, by wetetching (FIG. 17).

Then, a third on-substrate gate insulating film 122, a firston-substrate gate insulating film 123, a second metal gate film 124, afirst polysilicon film 125 and a third protective film 126 are laminatedon the entire surface of the memory cell region 100A and the peripheralcircuit region 100B (FIG. 18). As described above, the second Hf contentpercentage of the hafnium-containing compound in the first on-substrategate insulating film 123 is made higher than the first Hf contentpercentage of the hafnium-containing compound in the first buried gateinsulating film 116. It is preferred that the second Hf contentpercentage is made higher than the first Hf content percentage by 10 atm% or more. As the third on-substrate gate insulating film 122, forexample, a silicon oxide film formed by thermal oxidation may be used.As the third protective film 126, for example, a silicon oxide film maybe used.

Then, the second metal gate film 124, the first polysilicon film 125 andthe third protective film 126 are left only on the p-well 101 b of theperipheral circuit region 100B (FIG. 19). For example, After the p-well101 b is protected with a mask (not shown), the third protective film126 may be removed by dry etching, and the first polysilicon film 125and the second metal gate film 124 may be removed by wet etching.

Then, in a similar way to the process shown in FIG. 18, a secondon-substrate gate insulating film 128, a third metal gate film 129, asecond polysilicon film 130 and a fourth protective film 131 arelaminated on the entire surface of the memory cell region 100A and theperipheral circuit region 100B in addition to on the n-well 101 c of theperipheral circuit region 100B (FIG. 20). Therefore, ability of thetransistor can be improved because a material having high relativedielectric constant can be used in the peripheral circuit region. As thefourth protective film 131, for example, a silicon oxide film and asilicon oxynitride film may be used.

Then, in a similar way to the process shown in FIG. 19, the third metalgate film 129, the second polysilicon film 130 and the fourth protectivefilm 131 are left on the n-well 101 c of the peripheral circuit region100B (FIG. 21). For example, the fourth protective film 131, the secondpolysilicon film 130, the third metal gate film 129 and the secondon-substrate gate insulating film 128 are removed after a region abovethe n-well 101 c is protected with a mask (not shown). And, the thirdprotective film 126 in the p-well 101 b, the fourth protective film 131in the n-well 101 c and the third on-substrate gate insulating film 122are removed. In this way, a layered body of the first on-substrate gateinsulating film 123, the second metal gate film 124 and the firstpolysilicon film 125 is formed on the p-well 101 b, and a layered bodyof the first on-substrate gate insulating film 123, the secondon-substrate gate insulating film 128, the third metal gate film 129 andthe second polysilicon film 130 is formed on the n-well 101 c.

Then, in the memory cell region 100A, a part of the impurity diffusionlayer 101 a is exposed, and an impurity is implanted into the impuritydiffusion layer 101 a to form a high-concentration impurity diffusionlayer 101 d. Then, on the high-concentration impurity diffusion layer101 d, a layered body of a third polysilicon layer 134, a firstconductive film 135 and a third insulating film 136 is formed. In theperipheral circuit region 100B, the layered body of the thirdpolysilicon layer 134, the first conductive film 135 and the thirdinsulating film 136 is formed, but the layered body of the thirdpolysilicon layer 134, the first conductive film 135 and the thirdinsulating film 136 is laminated on a gate stack on the p-well 101 b andthe n-well 101 c (FIG. 22).

Then, a first interlayer insulating film 140, a contact pad 141, acapacitor 168, a second interlayer insulating film 145, a thirdinterlayer insulating film 146 and a protective film 148 and so on areformed to form a semiconductor device (FIGS. 2-4).

When the third on-substrate gate insulating film 122 is formed, forexample, by heat-treatment not less than 700 degrees Celsius, the memorycell region 100A is also exposed to thermal load. However, in thepresent disclosure, the hafnium-containing compound can be preventedfrom crystallizing by this heat-treatment because the first Hf contentpercentage of the hafnium-containing compound in the first buried gateinsulating film 116 of the memory cell region 100A is made low.Therefore, the increase of the equivalent oxide thickness in thetransistor of the memory cell region 100A, the increase of the gate leakcurrent, and the increase in the threshold voltage can be prevented, andthe on-state current can be increased. Furthermore, the increase of avariation in the threshold voltage can be restrained. Furthermore, ashort circuit by the crystallization of the hafnium-containing compoundalso can be prevented. And, an ability of the transistor of theperipheral circuit region 100B can be improved because the materialhaving high relative dielectric constant can be used without thecrystallization of the hafnium-containing compound in the peripheralcircuit region 100B.

For example, the present disclosure of the present application alsoincludes an invention of “a semiconductor device, comprising: a firstsource electrode and a first drain electrode which are formed on asemiconductor substrate; and a first buried gate insulating film whichis formed along an inner wall of a trench formed in the semiconductorsubstrate between the first source electrode and the first drainelectrode and whose relative dielectric constant is higher than arelative dielectric constant of silicon oxide; and a buried gateelectrode which is formed in the trench on the first buried gateinsulating film, has metal and functions as a word line.”

A further problem(s), object(s) and exemplary embodiment(s) of thepresent disclosure become clear from the entire of the presentdisclosure including claims and drawings.

The present disclosure, for example, can be applied to DRAM.

Preferred modes of each aspect are described below.

According to a preferred mode of the first aspect, the first Hf contentpercentage is lower than the second Hf content percentage.

According to a preferred mode of the first aspect, the first Hf contentpercentage is lower than the second Hf content percentage by 10 atm % ormore.

According to a preferred mode of the first aspect, thehafnium-containing compound is not crystallized in the first buried gateinsulating film even if the first buried gate insulating film isheat-treated at a temperature of 700 degrees Celsius or more.

According to a preferred mode of the first aspect, the first Hf contentpercentage is 10 atm % to 90 atm %.

According to a preferred mode of the first aspect, the semiconductordevice further comprises a second buried gate insulating film between aninner wall of a trench of the semiconductor substrate and the firstburied gate insulating film.

According to a preferred mode of the first aspect, the second buriedgate insulating film comprises a silicon oxide film or a siliconoxynitride film.

According to a preferred mode of the first aspect, a part of the secondtransistors in the peripheral circuit region further has/have a secondon-substrate gate insulating film having higher relative dielectricconstant than that of silicon oxide on the first on-substrate gateinsulating film.

According to a preferred mode of the first aspect, the second transistorfurther has a third on-substrate insulating film between thesemiconductor substrate and the first on-substrate insulating film.

According to a preferred mode of the first aspect, the thirdon-substrate insulating film comprises a silicon oxide film or a siliconoxynitride film.

According to a preferred mode of the first aspect, the semiconductordevice further comprises a cap buried insulating film which is buried inthe trench of the semiconductor substrate on the buried gate electrode.

According to a preferred mode of the first aspect, the firston-substrate gate insulating film is formed above a surface of thesemiconductor substrate.

According to a preferred mode of the second aspect, the first Hf contentpercentage is lower than the second Hf content percentage.

According to a preferred mode of the second aspect, the first Hf contentpercentage is lower than the second Hf content percentage by 10 atm % ormore.

According to a preferred mode of the second aspect, the first Hf contentpercentage is 10 atm % to 90 atm %.

According to a third aspect of the present disclosure, there is provideda method of manufacturing a semiconductor device. The method comprises:forming a trench in a semiconductor substrate of a memory cell region;forming a first buried gate insulating film which comprises hafnium andwhose relative dielectric constant is higher than a relative dielectricconstant of silicon oxide, along an inner wall of a trench; forming aburied gate electrode on the buried gate insulating film; forming afirst source electrode and a first drain electrode in the semiconductorsubstrate on both sides of the trench; forming a first on-substrate gateinsulating film which comprises hafnium and whose relative dielectricconstant is higher than a relative dielectric constant of silicon oxide,on a surface of the semiconductor substrate of the peripheral circuitregion; forming an on-substrate gate electrode on the first on-substrategate insulating film; and forming a second source electrode and a seconddrain electrode in the semiconductor substrate of both sides of theon-substrate gate electrode. The first buried gate insulating film andthe first on-substrate gate insulating film are formed so that a firstHf content percentage, which is a content percentage of hafnium in thefirst buried gate insulating film, is different from a second Hf contentpercentage, which is a content percentage of hafnium in the firston-substrate gate insulating film.

According to a preferred mode of the third aspect, the first Hf contentpercentage is lower than the second Hf content percentage.

According to a preferred mode of the third aspect, the first Hf contentpercentage is made lower than the second Hf content percentage by 10 atm% or more.

According to a preferred mode of the third aspect, the first Hf contentpercentage is set in 10 atm % to 90 atm %.

According to a preferred mode of the third aspect, the firston-substrate gate insulating film is formed after forming the firstburied gate insulating film.

According to a preferred mode of the third aspect, the method ofmanufacturing the semiconductor device further comprises forming a thirdon-substrate gate insulating film on the semiconductor substrate of theperipheral circuit region by heat-treatment after forming the firstburied gate insulating film and before forming the first on-substrategate insulating film.

According to a preferred mode of the third aspect, the heat-treatment isa heat-treatment of 700 degrees Celsius or more.

According to a fourth aspect of the present disclosure, there isprovided a semiconductor device, comprising: a memory cell region havinga first transistor, and a peripheral circuit region which is formedaround the memory cell region and has a second transistor, on asemiconductor substrate. The first transistor has a first sourceelectrode and a first drain electrode which are formed in thesemiconductor substrate, a first buried gate insulating film which isformed along an inner wall of a trench formed in the semiconductorsubstrate between the first source electrode and the first drainelectrode and whose relative dielectric constant is higher than arelative dielectric constant of silicon oxide, and a buried gateelectrode which is formed in the trench on the first buried gateinsulating film, comprises metal and functions as a word line.

According to a fifth aspect of the present disclosure, there is provideda method of manufacturing a semiconductor device, comprising: forming atrench in a semiconductor substrate of a memory cell region; forming afirst buried gate insulating film which comprises a hafnium-containingcompound and whose relative dielectric constant is higher than arelative dielectric constant of silicon oxide, along an inner wall ofthe trench; forming a buried gate electrode on the buried gateinsulating film; forming a first source electrode and a first drainelectrode in the semiconductor substrate on both sides of the trench;forming a first on-substrate gate insulating film which comprises ahafnium-containing compound and whose relative dielectric constant ishigher than a relative dielectric constant of silicon oxide on a surfaceof the semiconductor substrate of the peripheral circuit region; formingan on-substrate gate electrode on the first on-substrate gate insulatingfilm; and forming a second source electrode and a second drain electrodein the semiconductor substrate of both sides of the on-substrate gateelectrode.

DEFINITIONS

In the present disclosure, the following definitions are applied. (1)The term “on a (the) substrate” denotes “on”, “above”, “on the upperpart of” or “in” the substrate, and should not be understood excludingthe case of “in”. (2) Numerical values and numerical ranges disclosedand claimed herein are deemed to include all the intervening valuesand/or subranges, even if explicitly recited. The recitation of suchintervening values is redacted merely for the simplicity in thedisclosure. (3) The singular form or articles such as “a” and “the”represents single and/or plural. This is also valid based on thepriority disclosure in Japanese language which has inherently nodifference between singular form and plural form of the noun.

The semiconductor device and manufacturing method thereof of the presentdisclosure are explained based on the above exemplary embodiments, butare not limited to the above exemplary embodiments, and may include anymodification, change and improvement to the disclosed various elements(including each element of each claim, each element of each example,each element of each figure and others) within the scope of the presentdisclosure and based on the basic technical idea of the presentdisclosure. Within the scope of the claims of the present disclosure,various combinations, displacements and selections of disclosed elements(including each element of each claim, each element of each example,each element of each figure and others) are available.

What is claimed is:
 1. A semiconductor device, comprising: a memory cellregion having a first transistor, and a peripheral circuit region whichis formed around said memory cell region and has a second transistor, ona semiconductor substrate, wherein said first transistor comprises: afirst source electrode and a first drain electrode which are formed onsaid semiconductor substrate, a first buried gate insulating film whichis formed along an inner wall of a trench formed in said semiconductorsubstrate between said first source electrode and said first drainelectrode and whose relative dielectric constant is higher than arelative dielectric constant of silicon oxide, and a buried gateelectrode which is formed in said trench on said first buried gateinsulating film, comprises metal and functions as a word line; andwherein the said second transistor comprises: a second source electrodeand a second drain electrode which are formed on said semiconductorsubstrate, a first on-substrate gate insulating film which is formed ona surface of said semiconductor substrate between said second sourceelectrode and said second drain electrode and whose relative dielectricconstant is higher than a relative dielectric constant of silicon oxide,and an on-substrate gate electrode which is formed on said firston-substrate gate insulating film and comprises metal; said first buriedgate insulating film and said first on-substrate gate insulating filmcomprising a compound containing a metal element, wherein a first metalcontent percentage, which is a content percentage of the metal elementin said first buried gate insulating film, is different from a secondmetal content percentage, which is a content percentage of the metalelement in said first on-substrate gate insulating film.
 2. Thesemiconductor device according to claim 1, wherein said first metalcontent percentage is lower than said second metal content percentage.3. The semiconductor device according to claim 1, wherein said firstmetal content percentage is lower than said second metal contentpercentage by 10 atm % or more.
 4. The semiconductor device according toclaim 1, wherein said compound in said first buried gate insulating filmis not crystallized even if said first buried gate insulating film isheat-treated at a temperature of 700 degrees Celsius or more.
 5. Thesemiconductor device according to claim 1, wherein said first metalcontent percentage is 10 atm % to 90 atm %.
 6. The semiconductor deviceaccording to claim 1, wherein said first buried gate insulating filmcomprises hafnium silicate.
 7. The semiconductor device according toclaim 1, wherein said first buried gate insulating film has a thicknessranging from 1 nm to 3.5 nm.
 8. The semiconductor device according toclaim 1, further comprising: a second buried gate insulating filmbetween an inner wall of said trench of said semiconductor substrate andsaid first buried gate insulating film.
 9. The semiconductor deviceaccording to claim 8, wherein said second buried gate insulating filmcomprises a silicon oxide film or a silicon oxynitride film.
 10. Thesemiconductor device according to claim 1, wherein a part of said secondtransistors in said peripheral circuit region further has/have a secondon-substrate gate insulating film having higher relative dielectricconstant than that of silicon oxide on said first on-substrate gateinsulating film.
 11. The semiconductor device according to claim 10,wherein said second on-substrate gate insulating film comprises alumina.12. The semiconductor device according to claim 1, wherein said secondtransistor further has a third on-substrate insulating film between saidsemiconductor substrate and said first on-substrate insulating film. 13.The semiconductor device according to claim 12, wherein said thirdon-substrate insulating film is a silicon oxide film or a siliconoxynitride film.
 14. The semiconductor device according to claim 1,further comprising: a cap buried insulating film which is buried in saidtrench of said semiconductor substrate on said buried gate electrode.15. The semiconductor device according to claim 1, wherein said firston-substrate gate insulating film is formed above a most upper surfaceof said semiconductor substrate.
 16. The semiconductor device accordingto claim 1, wherein said first on-substrate gate insulating filmcomprises hafnium oxide or hafnium silicate.
 17. A semiconductor device,comprising: a first transistor and a second transistor on asemiconductor substrate, wherein said first transistor comprises: afirst gate insulating film which is formed along an inner wall of atrench formed in said semiconductor substrate and whose relativedielectric constant is higher than a relative dielectric constant ofsilicon oxide, and a first gate electrode which is buried in said trenchand formed on said first gate insulating film, and comprises metal; andwherein said second transistor comprises: a second gate insulating filmwhich is formed on a most upper surface of said semiconductor substrateand whose relative dielectric constant is higher than a relativedielectric constant of silicon oxide, and a second gate electrode whichis formed on said second gate insulating film and comprises metal; saidfirst gate insulating film and said second gate insulating filmcomprising a compound containing a metal element, wherein a first metalcontent percentage, which is a content percentage of the metal elementin said first gate insulating film, is different from a second metalcontent percentage, which is a content percentage of the metal elementin said second gate insulating film.
 18. The semiconductor deviceaccording to claim 17, wherein said first metal content percentage islower than said second metal content percentage.
 19. The semiconductordevice according to claim 17, wherein said first metal contentpercentage is lower than said second metal content percentage by 10 atm% or more.
 20. The semiconductor device according to claim 17, whereinsaid first metal content percentage is 10 atm % to 90 atm %.